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SMBus/I 2 C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Table 14. CLA1 (P6–P9) Configuration Register Setting (0x29) (continued)
FUNCTION
D5
D4
REGISTER BIT
D3 D2
D1
D0
2 input AND/OR P6 and P8 noninverted
0
0
2 input AND/OR P6 and P8 inverted
2 input AND/OR P6 inverted and P8
1
1
0
0
X
1
0
1
2 input AND/OR P6 and P8 both inverted
2 input AND/OR P7 and P8 noninverted
1
0
0
1
2 input AND/OR P7 and P8 inverted
2 input AND/OR P7 inverted and P8
1
0
1
1
1
0
0
X
2 input AND/OR P7 and P8 both inverted
1
1
Table 15. Output P9 and Cascade P5
Input Configuration
Table 17. Configurable Logic-Array Lock
Register (0x71)
BIT
D7
D6
LOGIC LEVEL
0
1
0
1
FUNCTION
Cascade input noninverted
Cascade input inverted
Output noninverted
Output inverted
REGISTER
CLA0 and CLA1 configurable
logic lock
CLA0 is not locked
CLA0 is locked
CLA1 is not locked
REGISTER DATA
D7–D2 D1 D0
CLA1 CLA0
— X 0
— X 1
—
0
X
Table 16. Configurable Logic-Array
CLA1 is locked
—
1
X
Enable Register (0x70)
REGISTER
REGISTER DATA
D7–D2 D1 D0
CLA0 and CLA1 configurable
logic enable
CLA1
CLA0
Ports P2–P5 are GPIO ports
Ports P2–P5 are configurable logic
CLA0
Ports P6–P9 are GPIO ports
Ports P6–P9 are configurable logic
CLA1
—
—
—
—
X
X
0
1
0
1
X
X
______________________________________________________________________________________
19
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